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T ent UC OD lacem R E P Rep LET ded SO n O B o mme c e oR
HIP5063
August 1998 File Number 3209.2
Power Control IC Single Chip Power Supply
The HIP5063 is a complete power control IC, incorporating both the high power DMOS transistor, CMOS logic and low level analog circuitry on the same Intelligent Power IC. This IC allows the user maximum flexibility in implementing high frequency current controlled power supplies and other power sources. Special power transistor current sensing circuitry is incorporated that minimizes losses due to the monitoring circuitry. Over-temperature detection circuitry is incorporated within the IC to monitor the chip temperature. As a result of the power DMOS transistor's current and voltage capability (10A and 60V), power supplies with output power capability up to 100 watts are possible.
Features
* Single Chip Current Mode Control IC * 60V, 10A On-chip DMOS Transistor * Thermal Protection * 1MHz Operation - External Clock * Output Rise and Fall Times ~ 3ns * Simple Implementation of High-Speed Current Mode Controlled Regulators and Power Amplifiers * Designed for 10V to 45V Operation
Applications
* Single Chip Power Supplies * Current Mode PWM Applications * Distributed Power Supplies * Multiple Output Converters
Ordering Information
PART NUMBER HIP5063DY HIP5063DW TEMPERATURE RANGE 0oC to +85oC 0oC to +85oC PACKAGE 21 Pad Chip Wafer
* Wideband Power Amplifiers for Motor Control
Chip
(10) AGND (11) DGND (12) VDDP S (13) (7) TMON (1) VCMP (6) COOL (5) CLCK (2) VDDA (3) VDDD (4) FLLN (8) IRFO (9) IRFI D (14)
VDDP (21)
S (19)
S (17)
D (20)
D (18)
NOTE: Unused pads are for trim and test. 122 mils x 126 mils (3.1mm x 3.2mm)
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2002. All Rights Reserved
D (16)
S (15)
HIP5063 Simplified Block Diagram
4H VIN = 36V 12V 3.8H FLLN 1MHz CLOCK CLCK TMON VDDA CONTROL LOGIC VDDD GATE DRIVERS S VDDP D 0.1F 0.88F 33F 5.1V OUTPUT 0.66F 3H 0.1F
THERMAL MONITOR
HIP5063 + VCMP + 5.1V REF
COOL AGND DGND IRFI IRFO
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TYPICAL SEPIC APPLICATION CONFIGURATION
Functional Block Diagram
CLCK VDDA VDDD VDDP
VDDA
BIAS CIRCUITS DRAIN
50A FLLN S FLIP-FLOP R Q FAST RESET THERMAL MONITOR 18K CONTROL & BLANKING LOGIC CURRENT MONITORING AMP GATE DRIVERS
TMON
SOURCE
COOL
VCMP
+ -
IREF AGND IRFO IRFI DGND
EXTERNAL CURRENT SCALING RESISTOR IPEAK(DMOS DRAIN CURRENT) = 4500 x IREF (mA)
2
HIP5063
Absolute Maximum Ratings
DMOS Drain Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 60V DMOS Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20A DC Logic Supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 16V Output Voltage, Logic Outputs . . . . . . . . . . . . . . . . . . . -0.3V to 16V Input Voltage, Analog and Logic. . . . . . . . . . . . . . . . . . -0.3V to 16V Operating Junction Temperature Range . . . . . . . . . .0oC to +110oC Storage Temperature Range . . . . . . . . . . . . . . . . . -55oC to +150oC
Thermal Information
Thermal Resistance JC (Solder Mounted to . . . . . . . . . . . . . . . . . . . . . . . . . 3oC/W Max 0.050" Thick Copper Heat Sink) Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . +110oC (Controlled By Thermal Shutdown Circuit)
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Electrical Specifications VDDA = VDDD = VDDP = 12V, TJ = 0oC to +110oC; Unless Otherwise Specified
SYMBOL DEVICE PARAMETERS I+ Supply Current External Clock Input = 1MHz 14 mA PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
DMOS TRANSISTORS rDS(on) IDSS Drain-Source On-State Resistance Drain-Source Leakage Current I Drain = 5A, TJ = +25oC Drain to Source Voltage = 60V 0.13 A
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1
100
CURRENT CONTROLLED PWM |VIO| VCMP IGAIN RIRFI tRS MCPW Buffer Offset Voltage (VCMP - VIRFO) IPEAK (DMOSDRAIN)/IIRFI IRFI Resistance to GND Current Comparator Response Time (Note 1) Minimum Controllable Pulse Width (Note 1) Minimum Controllable DMOS Peak Current (Note 1) IRFO = 0mA to -5mA, VCMP = 0.2V to 7.6V I (DMOSDRAIN)/t = 1A/ms IRFI = 2mA I (DMOSDRAIN)/t > 1A/ms 125 mV
3.8 150 -
30
4.9 360 -
A/mA ns
25
50
100
ns
MCPI
200
400
800
mA
CLOCK VTH CLCK VTH FLLN IFLLN CLCK Input Threshold Voltage FLLN Input Threshold Voltage FLLN Pull-Up Current VFLLN = 0V 4 4 -70 -50 8 8 -30 V V A
THERMAL MONITOR TEMP Substrate Temperature for Thermal Monitor to Trip (Note 1) COOL Leakage Current COOL Low-State Voltage TMON pin open 105 135
oC
ILEAK COOL VCOOL NOTE:
VCOOL = 12V ICOOL = 2mA, TJ > +125oC
-
-
1 0.4
A V
1. Determined by design, not a measured parameter.
3
HIP5063 Pin Descriptions
PAD NUMBER 1 DESIGNATION VCMP DESCRIPTION This is the input terminal from an external error amplifier. A MOS input voltage follower buffers this terminal. The buffer output is the IRFO terminal. The external error amplifier may be either an operational amplifier or a transconductance amplifier like the CA3080. This node may be used for both gain and frequency compensation of the control loop. This is the analog supply input. An external 12V supply is required. Voltage input for the chip's digital circuits. One pad of two clocking terminals. This terminal has an external 50A pull-up current that allows the terminal to be floated or be left open. With FLLN high, (open or tied to VDDD), the ON cycle will start wiith the falling edge of the CLCK input. With FLLN low or grounded, the DMOS ON cycle will start on the rising edge of the CLCK input. The other clock input pad. An external clock is applied to this terminal. This terminal has no pullup current or resistance. See FLLN above for phasing information. Over-temperature indication is provided at this pad. When the chip temperature is below the thermal threshold, the open drain DMOS transistor is in the high impedance state. When the thermal threshold is exceeded, COOL is held low. This is the thermal shut down pad than can be used to disable the thermal shutdown circuit. By returning this pad to V DDA or 12V the function is disabled. Returning this pad to ground will enable the thermal monitor function. Thermal threshold occurs at a nominal junction temperature of +125oC. A resistor placed between this pad and IRFI converts the VCMP signal to a reference current for the current sense comparator. The cycle by cycle peak current is set by the value to this resistor according the the equation: IPEAK = 4500 x VCMP/R. Where IPEAK is in amperes and R is the value of the external resistor in ohms. A maximum VCMP of 8V and a resistor of 1800 will keep the drain current below the absolute maximum specification of 20A. See IRFO. Analog ground. Digital ground. These pads are used to decouple the high current pulses to the output driver transistors. The capacitor should be at least a 0.1F chip capacitor placed close to this pad and the DMOS source pads. Source pads of the DMOS power transistor. Drain pads of the DMOS power transistor.
2 3 4
VDDA V DDD FLLN
5 6
CLCK COOL
7
TMON
8
IRFO
9 10 11 12 & 21
IRFI AGND DGND VDDP
13, 15, 17, 19 14, 16, 18, 20
S D
4

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